This application claims the priority benefit of Taiwan application serial no. 90117175, filed Jul. 13, 2001.
1. Field of the Invention:
This invention relates to signal processing technology, and more particularly, to an oversampling circuit and method.
2. Description of Related Art:
Serial link technology is utilized in communications systems, can offer a data transmission rate up to one billion bits per second and is also low cost to implement. Due to these benefits, the serial link technology is widely used in radio transceivers, computer-to-computer communication, and computer-to-peripheral communication.
FIG. 1 shows a conventional transceiver which utilizes serial link technology (for details, please refer to IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. MAY 5, 1988, xe2x80x9cA 0.5 xcexcm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery (Using Oversamplingxe2x80x9d, Chih-Kong Ken Yan, Ramin Farjad-Rad, Mark A. Horowitz). As shown, the transceiver 100 includes an oversampling circuit 102 whose input end (Data In) is used to receive a 4-Gbps serial data stream, and which is capable of converting the serial data into 8-bit parallel format. In order to obtain the correct transition of each bit, the oversampling circuit 102 utilizes a sampling rate three times the bit rate of the input data. Therefore, the PLL (phase-locked loop) circuit 104 should output 24 sampling pulses to the oversampling circuit 102 for each output byte.
FIG. 2 shows a conventional oversampling circuit 200 (which can be used to serve as the oversampling circuit 102 shown in FIG. 1). As shown, this oversampling circuit 200 includes 24 MOSFETs, each MOSFET has a gate connected to the PLL circuit 104 shown in FIG. 1 to receive one of the 24 output sampling pulses from the PLL circuit 104; i.e., the first MOSFET 202 has its gate connected to receive the first sampling pulse "PHgr"1 from the PLL circuit 104; the second MOSFET 204 has its gate connected to receive the second sampling pulse "PHgr"2; and so forth the last MOSFET 206 having its gate connected to receive the 24th sampling pulse "PHgr"24.
Referring back to FIG. 1, since the input end (Data In) of the oversampling circuit 102 receives a 4-Gbps serial data stream, the period of each bit is 250 ps (picosecond). Therefore, the use of the triple sampling rate would result in a phase difference xcex94t as follows:
xcex94t=250/3=83 ps
The pulse sequencing diagram of the sampling pulses ("PHgr"1xcx9c"PHgr"24 is shown in FIG. 3. The period T of each of the sampling pulses "PHgr"1xcx9c"PHgr"24 is 250 ps, and the phase difference between two successive sampling pulses is xcex94t=83 ps. These 24 sampling pulses "PHgr"1xcx9c"PHgr"24 are used for the sampling of one byte of data; wherein the first three sampling pulses "PHgr"1xcx9c"PHgr"3 are used for the sampling of the first bit in the byte, the second three sampling pulses "PHgr"4xcx9c"PHgr"6 are used for the sampling of the second bit in the byte, and so forth the last three sampling pulses "PHgr"22xcx9c"PHgr"24 being used for the sampling of the eighth bit in the byte.
Therefore, one byte of data is generated for each cycle of the 24 sampling pulses "PHgr"1xcx9c"PHgr"24.
Each cycle of the 24 sampling pulses "PHgr"1xcx9c"PHgr"24 will respectively cause the 24 transmission gates of the MOSFETs in the oversampling circuit 200 of FIG. 2 to be switched ON. In this case, the fan-out loading of the oversampling circuit 200 is the loading of the 24 transmission gates. If the sampling rate is five times the bit rate, the oversampling circuit then needs 40 transmission gates; and in this case, the fan-out loading is the loading of the 40 transmission gates. Fundamentally, a larger sampling rate will require a larger fan-out loading. However, an overly large fan-out loading would cause the oversampling circuit to lose its fan-out capability.
One solution to the foregoing problem is to use a multi-stage oversampling circuit 400 shown in FIG. 4, which needs 27 sampling pulses rather than 24 for each cycle of byte. As shown, these 27 sampling pulses are denoted by ("PHgr"1,1xcx9c"PHgr"1,8, "PHgr"2,1xcx9c"PHgr"2,8, "PHgr"3,1xcx9c"PHgr"3,8, "PHgr"F1xcx9c"PHgr"F3); wherein "PHgr"1,1xcx9c"PHgr"1,8 are applied to the respective gates of 8 MOSFETs (401, 402, . . . , 403); "PHgr"2,1xcx9c"PHgr"2,8 are applied to the respective gates of 8 MOSFETs (405, 406, . . . , 407); "PHgr"3,1xcx9c"PHgr"3,8 are applied to the respective gates of 8 MOSFETs (409, 410, . . . , 411); and "PHgr"F1xcx9c"PHgr"F3 are applied to the respective gates of 3 MOSFETs (404, 408, . . . , 412). This requires the PLL circuit 104 to generate 27 sampling pulses.
FIG. 5 shows the pulse sequencing diagram of the 27 sampling pulses "PHgr"1,1xcx9c"PHgr"1,8, "PHgr"2,1xcx9c"PHgr"2,8, "PHgr"3,1xcx9c"PHgr"3,8 and "PHgr"F1xcx9c"PHgr"F3. As shown, the period T of each of the 27 sampling pulses is T=250 ps, and the phase difference between two successive pulses in "PHgr"1,1xcx9c"PHgr"1,8, "PHgr"2,1xcx9c"PHgr"2,8 and "PHgr"3,1xcx9c"PHgr"3,8 is xcex94t1=83 ps. The sampling pulse "PHgr"F1 appears at logic-HIGH state for a period of 7*xcex94t1+xcex94t2, which causes the MOSFET 404 to be switched ON. Then, the 8 MOSFETs (401, 402, . . . , 403) are successively switched ON by "PHgr"1,1xcx9c"PHgr"1,8, allowing them to sample the input serial data. The sampling pulse "PHgr"F1 is switched from logic-HIGH back to logic-LOW by a time lag of xcex94t2 after the transition of the last sampling pulse "PHgr"1,8 from logic-LOW to logic-HIGH. This can help ensure that the last MOSFET 403 has been switched ON when the MOSFET 404 is switched OFF.
After "PHgr"F1 has been switched from logic-HIGH to logic-LOW, "PHgr"F2 must be switched from logic-LOW to logic-HIGH at an earlier time than or at the same time as "PHgr"2,1. This can help prevent the condition of the MOSFET 405 being switched ON while the MOSFET 408 is still in OFF state. Otherwise, it would cause loss of data at the MOSFET 405. Therefore, "PHgr"F2 should remain at logic-HIGH for a period of 7*xcex94t1+xcex94t2 (the same as "PHgr"F1).
When the sampling pulse "PHgr"F2 appears at logic-HIGH, it causes the MOSFET 408 shown in FIG. 3 to be switched ON. Then, the 8 MOSFETs (405, 406, . . . , 407) are successively switched ON by "PHgr"2,1xcx9c"PHgr"2,8 allowing them to sample the input serial data. The sampling pulse "PHgr"F2 is switched from logic-HIGH back to logic-LOW by a time lag of xcex94t2 (xcex94t2 less than xcex94t1) after the transition of the last sampling pulse "PHgr"2,8 from logic-LOW to logic-HIGH. This can help ensure that the last MOSFET 407 has been switched ON when the MOSFET 408 is switched OFF.
The operations of the sampling pulses ("PHgr"3,1xcx9c"PHgr"3,8, "PHgr"F3) are similar to the operations of ("PHgr"1,1xcx9c"PHgr"1,8, "PHgr"F1) and ("PHgr"2,1xcx9c"PHgr"22,8, "PHgr"F2), so description thereof will not be repeated.
The forgoing multi-stage oversampling circuit 400 shown in FIG. 4 can solve the earlier-mentioned fan-out problem of the conventional oversampling circuit by providing an additional stage of MOSFET circuit, i.e., the three MOSFETs 404, 408, 412. This first stage of MOSFET circuit (404, 408, 412) can separate the input end (Data In) from the second stage of MOSFET circuit [(401, 402, . . . , 403), (405, 406, . . . , 407), (409, 410, . . . , 411)], thus allowing the outputs of the first stage of MOSFET circuit to be directly fan-out to the output loading of the second stage of MOSFET circuit.
One drawback to the forgoing multi-stage oversampling circuit 400 shown in FIG. 4, however, is that the timing for the sampling pulse used to switch the first stage of MOSFET circuit and the second stage of MOSFET circuit should be highly precisely controlled; otherwise, if any of the MOSFET in the first stage slightly lag behind, it would undesirably cause loss of data at the second stage of MOSFET circuit. This timing control, however, is quite difficult to achieve, and thus the probability of data loss is high.
It is therefore an objective of this invention to provide a new oversampling circuit and method, which can reduce the number of fan-outs at the output loading of the transmission gate circuit, and which allows a larger error margin in the timing of the sampling pulses.
The oversampling circuit according to the invention comprises an array of transmission gates arranged into N cascaded stages of main sampling circuits, each stage of main sampling circuit being composed of M parallel layers of sub-sampling circuits, where N, M are each an integer number; each transmission gate has an input end, an output end, and a control port; and the respective control ports of all the transmission gates are connected to a predefined sequence of sampling pulses; wherein the transmission gates in the first stage of main sampling circuit are arranged in parallel and whose input ends are connected to receive the input serial data stream and whose output ends are each cascaded to one sub-sampling circuit in the next stage which is composed of a plurality of transmission gates arranged in parallel in a number equal to the number of bits in the parallel data format and whose input ends are connected together to the output end of the transmission gate in the previous stage of main sampling circuit; and wherein in the next stage of main sampling circuits, at least one of the transmission gates in one layer of sub-sampling circuit has its output end connected to one of the transmission gates in the next layer of sub-sampling circuit; and at least one of the transmission gates in the last layer of sub-sampling circuit has its output end connected to one of the transmission gates in the first layer of sub-sampling circuit.
The oversampling method according to the invention is used on an oversampling circuit composed of an array of transmission gates arranged into N cascaded stages of main sampling circuits, each stage of main sampling circuit being composed of M parallel layers of sub-sampling circuits, where N, M are each an integer number; each transmission gate has an input end, an output end, and a control port. The oversampling method of the invention comprises the steps of: arranging the transmission gates in the first stage of main sampling circuit in parallel and whose input ends are connected to receive the input serial data stream and whose output ends are each connected to one sub-sampling circuit in the next stage which is composed of a plurality of transmission gates arranged in parallel in a number equal to the number of bits in the parallel data format and whose input ends are connected together to the output end of the transmission gate in the previous stage of main sampling circuit; connecting at least one of the output ends of the transmission gates in one layer of sub-sampling circuit to one of the output ends of the transmission gates in the next layer of sub-sampling circuit; and connecting at least one of the output ends of the transmission gates in the last layer of sub-sampling circuit to one of the output ends of the transmission gates in the first layer of sub-sampling circuit, applying a predefined sequence of sampling pulses to the respective control ports of the transmission gates in each stage of main sampling circuit; and as one of the transmission gates in each stage of main sampling circuit is switched ON, applying a predefined sequence of sub-sampling pulses to the respective control ports of the transmission gates in the cascaded sub-sampling circuit.
The oversampling circuit and method of the invention can help reduce the number of fan-outs. Moreover, the invention allows a greater error margin that allows the pulse generation and sequencing to be easier to realize than the prior art.